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Additional resources for 57.Solid State Circuits
1994 IEEE. BiCMOS MEMORY CIRCUITS performance. Despite significant efforts by many groups (15), true active pull-down circuits remain fickle. They are either process intolerant or require special devices or supply voltages. Furthermore, they nullify one of the advantages of current-steering logic: low noise. , eight drivers can share the same pull-down current on a three-bit predecoded signal). In contrast, in an 8-bit data bus, there is no interrelationship between the bits and hence only a true active pull-down could be used.
Such a technique significantly lowers the emitter-follower static power dissipation while potentially improving Out R2 Q2 In0 In1 Vb3 Shared Vcs gnd gnd R gnd (b) Figure 7. Two ECL NOR gates with emitter-follower current sharing: (a) diode, (b) active (3). The current sharing permits each decoder to be powered up for maximum speed without exceeding the overall memory’s power budget. Reprinted with permission from ‘‘A Subnanosecond 64kb BiCMOS SRAM,’’ Santoro, Tavrow, and Bewick, Proc. BCTM. 1994 IEEE.
292 BiCMOS LOGIC CIRCUITS accelerates the operation of the CMOS logic circuits; this is verified by evaluating the CMOS parallel adders with BiCMOS driver cells. From HSPICE simulations shown in Fig. 547% in the case of the 66-bit adder. The results are tabulated in Table 2. Cn Cn – 1 R(n – m) R(m) Using BiCMOS P and G Subcells in Parallel Adders Figure 19 shows the implementation of a 32-bit parallel adder that uses BiCMOS driver cells to shorten the critical path delay, and the propagation delay through the leftmost vertical path of the carry-propagation circuit is shortened by introducing BiCMOS subcells in the critical path as shown by the bold path of arrows.