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If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during the four last steps to avoid these problems. 6 MHz) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.

In this mode, the ADC samples and updates the Data Registers continuously. Clearing this bit (zero) will terminate Free Running mode. If active channels are used (MUX2 in ADMUX set), the 47 1187F–AVR–06/05 channel must be selected before entering Free Running mode. Selecting an active channel after entering Free Running mode may result in undefined operation from the ADC. • Bit 4 – ADIF: ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the Data Registers are updated.

The different prescaling values and their corresponding time-out periods are shown in Table 15. Table 15. Watchdog Timer Prescale Select WDP2 WDP1 WDP0 Time-out Period 0 0 0 16K cycles 0 0 1 32K cycles 0 1 0 64K cycles 0 1 1 128K cycles 1 0 0 256K cycles 1 0 1 512K cycles 1 1 0 1,024K cycles 1 1 1 2,048K cycles 35 1187F–AVR–06/05 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. 2 ms, depending on the frequency of the calibrated RC Oscillator. See Table 16 for details.

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